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Slache
Beginner
65 Views

MAX10 Damaged with clk pin pulled down

Hello,

On my new design, I observe recurring FPGA MAX10 failures. The board has 6 similarly polarized FPGAs 10M08SCU169I7G . The FPGAs are programmed correctly, run fine for a few hours and then one of the 6 breaks for no apparent reason. After replacement, the card is functional again and I no longer observe any failure.
On two occasions, I observed a similar failure, the clock signal seems to be pulled low by the FPGA. The clock pin used is a CLK0n, or CLK1p used in 0-3.3V and configured in 3.3 V Schmitt Trigger

I did not observe any other pins pulled low.

I would focus more on the production problems of the card, however, I am surprised to observe the same failure several times. Do you know of any problem of this type? Do you have any leads to guide us?

Thank you

 

 

 

 

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1 Reply
JonWay_C_Intel
Employee
38 Views

You might want to

1) Check if there is any chance you have violated the absolute max spec: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf...(Table 4)

2) Check if it could be due to ESD.