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MAX10 Discerete RSU(Remote System Upgrade) Implementation

jozephka99
New Contributor II
717 Views

Hi,

I have questions about RSU.  I want to do a remote system upgrade discrete implementation (without Nios II) with uart. I watched the Intel's RSU course but I can't built the RSU anyway. I do the uart serial interface, ram and dual configuration IPs in manually but I dont understand how we can upload .rpd files into CFM section of FPGA. I can write ufm also but this don't help of course. I don't want to use Nios II softcore but I can use if I have to. In the relevant Intel course about RSU they said I need a state machine and configuration logic but they don't go further and tell how exactly I built the discrete RSU implementation or they didn't share any example of it. If you know how I can do that or you have an example project I'll be very happy if you share these informations with me.

@Altera_Forum 

0 Kudos
12 Replies
Ash_R_Intel
Employee
701 Views

Hi,

There is some example designs available on Intel website like this one:

I2C Remote System Update Example | Design Store for Intel® FPGAs

This one includes an I2C interface with NIOS processor. You may replace with UART IP, if you will.


You can also look into Remote Update Intel FPGA IP User Guide. Though it does not support MAX 10, but you can take some reference from there.


Regards.


jozephka99
New Contributor II
691 Views

Thanks, I saw that design example before. But in this example requires 2 FPGA for communicating with i2c because Quartus don't allow to flash the code in the irrelevent device. I have 1 FPGA and it is 10M08. There is very common example such as AN741 but in that example they use Nios II and they boot it from qspi they said it is because of they cannot boot Nios II from the on-chip memory because the on-chip already used by FPGA to store RSU files. But my mind confused here because RSU stored in CFM sectors but Nios II boot from UFM sectors of on-chip memory. How can they get mixed? There is plenty options to boot Nios II but I don't know exactly which one works in my FPGA but I'll try it anyway.

Ash_R_Intel
Employee
643 Views

Hi,


Please refer the example provided in the below link. It is based on I2C serial link. If you want, you may replace it with any other interface.


https://fpgacloud.intel.com/devstore/platform/14.1/Standard/max-10-i2c-to-rsu/


Regards.


jozephka99
New Contributor II
635 Views
Ash_R_Intel
Employee
627 Views

Please do a right-click and 'Save link as'.


Regards.


jozephka99
New Contributor II
615 Views

Hi again,

I download, upgrade and run the project that you linked. But I can't find where is the main code for doing the job. I just find bunch of IP's and their wires each other. Where is the state machine, or main logic functions?

Thank you for your helps @Ash_R_Intel .

茫于000
Beginner
604 Views

我使用的是单镜像非压缩模式,IP生成的时候选择这个项目,在编译工程里的器件里选择内部下载配置,也选择单镜像非压缩模式。生成的pof下载文件转换成rpd格式。

记住程序只能下载到CFM里,一般是SECTOR4和SECTOR5,所以这两个块都得配置成读写。然后就把要下载的rpd数据通过AVMM接口写入到CFM里,注意waitrequest信号的控制,写的时候拉高,写完后拉低再更新下一个要写的数据。 还要注意大小端,rpd文件里以hex格式打开后,字节需要按照bit更换大小端。

jozephka99
New Contributor II
594 Views

I can't understand your message. What language is this?

茫于000
Beginner
587 Views

where are you from ? I'm chinese.

jozephka99
New Contributor II
581 Views
atattyman
Beginner
212 Views

Hi,

 

I would also like to perform an RSU on a Max10 device, but can find very little information on how to do this using a discreet logic side implementation. Only using Nios which I have no experience with, and I'm not sure it will work on our hardware since we have no additional flash available.

 

Were you ever able to find any useful examples or help?

 

Kind regards.

AT.

 

 

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