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In the bootloader project I create a pof file with two sof files.
The first sof file - the bootloader project, the second one - the main project. At the same time I generate rpd files. From version 16 Quartus generates 2 separate rpd files - for CFM0 and CFM1 sections.
Then I burn the pof file with byte bluster. When I select pin CONGIG_SEL=1 - main runs, when CONGIG_SEL=0 bootloader runs. All good!
Now I burn the generated rpd_cfm1 file serially with the bootloader - and main doesn't run.
So I compared some addresses in SFM1 section - after burning with byte bluster and after burning rpd file - all looks the same. I display only 3 bytes of every word cause I don't have enough 7-segments.
================== ID3 =================
GOOD output_file_both_big_cfm1_auto.rpd
ADDRESS
16384 FF E2 FF FF E2 FF
16385 FF 92 43 FF 92 43
16386 FF 42 DF FF 42 DF
16387 A8 75 00 A8 75 00
16388 FF FF FF FF FF FF
16389 FF FF FF FF FF FF
16390 FF FF FF FF FF FF
16584 00 00 18 00 00 18
16585 00 00 00 00 00 00
18000 00 05 64 00 05 64
20000 00 00 00 00 00 00
40000 04 40 14 04 40 14
40001 14 C8 82 14 C8 82
40002 96 40 00 96 40 00
40100 42 A1 80 42 A1 80
40400 40 00 00 40 00 00
40800 41 87 8A 41 87 8A
40801 51 76 46 51 76 46
40802 06 65 32 06 65 32
40900 00 00 00 00 00 00
50000 43 12 41 43 12 41
50100 71 18 21 71 18 21
50120 10 00 00 10 00 00
50220 71 12 40 71 12 40
50420 70 11 00 70 11 00
50900 70 75 6D 70 75 6D
114687 FF FF FF FF FF FF
================== ID4 ================
ALL FF
What is going on?
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can I know when you create the rpd files did you follow as per the max 10 configuration guide steps given in below link page : 39/66
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf
Is endianess set correct ?
Thank you ,
Regards,
Sree
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Yes. I set a Big endian option as I was told. Otherwise I have to reverse every byte before writing it to flash.
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Can I know your quartus version ? also can you try below link for the converted rpd file
https://www.intel.la/content/www/xl/es/programmable/support/support-resources/knowledge-base/component/2018/while-loading---cof-file--during-rpd-file-creation--in-quartus--.html
There is issue in the quartus 18.0 and 18.1 version that RPD endianness settling not loading correctly.
Thank you ,
Regards,
Sree
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My version is 16.0. If I set Little endian - I see the difference while comparing register values - burned with a pof and burned with a rpd.
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sorry i didnt notice your update ; can I know did you get chance to find the issue ?
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The issue remains - when I download the cfm1_auto.rpd serially - the second image doesn't run.
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hmmm...can you send me the design files , let me try it on my side ..
I have one max 10 dev kit ...
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Thanks a lot. I found a bug in my program. Now it's OK.
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ok..thank you :)
Regards,
Sree

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