MAX10 GPIO Lite DDR Input Error

[_MZ_]

Salam

   I am working on MAX10M25SCE144I7G FPGA and instantiate a DDR input at pin 46 using the IP Catalog Wizard. But the fitter gives the following error:

"Error (171000): Can't fit design in device".

   I tried some possible options to get rid of this issue but i am still not successful. Any help would be appreciable.

Thanks

Z.

[AminT_Intel]

Hello,

You probably received that error due to out of specs setting. Please refer to our Max 10 documents on your design. You can refer to these two documents to begin with: 

1. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf

2. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf

Thanks

[_MZ_]

Thanks for your reply.

I have read all possible related documents but haven't find any information that DDR input is not supported at this specific pin. Interestingly other pins around this pin i can use as DDR inputs but this specific pin not. So as a last resort i have ended up on this forum for any precise clue/information.

[AminT_Intel]

Hello,

Have you checked other specs as well? The device IO standards, range of voltage, etc? That could give the same error as well

Thank you

[AminT_Intel]

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[AminT_Intel]

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[AminT_Intel]

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[_MZ_]

Yes everything checked. Pin 46 is is present in Bank 3 and all the banks are provided with 3.3V and in the Pin Planner it is set to 3.3-V LVCMOS. This input is interfaced with a chip and receives data.

[_MZ_]

So no answer/solution?