Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19098 Discussions

MAX10 Input PLL clock Rise Time/Fall Time requirment.

PG_N
Beginner
689 Views

Hi 

 

I am Using 10M08SCM153I7G.

 

What is the Rise Time / Fall Time requirement of the Input clock to max10.

Consider i am connecting external clock (50MHz - Oscillator) to CLK0P/DIFFIO_RX_L18P pin of max10 

M10 Clock.png

 

Regards

Prashanth Kumar G N

0 Kudos
1 Reply
JonWay_C_Intel
Employee
151 Views

Hi @PG N​ 

Rise fall time is does not affect PLL functionality. There is no requirement for rise fall time.

Reply