Hello there,I'm using the 10M08SCE144A7G FPGA. In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (signal PLL_L_CLKOUTp of the FPGA) to give the clock to these 3 converters. There is only 1 output of this type with this FPGA. I'll like to know if there is any recommendations using this output signal to fed 3 diferents Analog to Digital Converters ? (fanout , layout for exemple) Is this a good way to do it ? Maybe driving the PLL output to 3 diferents standard fast I/O pins (1 pin for 1 DAC) is a better design ? Thank you for your help. Julien.
Hi JDL,The MAX 10 PLLs can drive out to any regular I/O pin through the GCLK. You can refer to the MAX10 PLL user guide: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_clkpll.p... Each PLL generates five clock outputs through the c[4..0] counters. Even though only the C0 output counter can feed to the dedicated external clock outputs without going through the GCLK, other output counters can feed other I/O pins through the GCLK. So you should be able to feed the PLL output to I/O pins. Regards, nyusof (This message was posted on behalf of Intel Corporation)
Is it a high frequency clock? If it's not too high it shouldn't be a problem to output the clock on a regular I/O instead of a dedicated PLL output. It is just a bit slower.If you have problems meeting timing constraints with that solution, you can also use a DDS output, clocked with the PLL clock you want to export, and with the two SDR inputs set to 0 and 1. It will generate a signal with the same frequency, and usually a shorter delay than when connecting the clock directly to the I/O pin. If possible I'd recommend that you build a (at least) minimal Quartus project with your timing requirements and verify that you can meet them before committing the pins assignments on the PCB layout.