Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

MAX10 RSU

atattyman
Beginner
368 Views

Hello,

 

My goal is to implement RSU on a max 10 device via the easiest method, performed by a separate uC over some serial interface in which I'm free to define.

 

My FPGA design is all discreet logic, manually written in VHDL, I have no Nios implementation and have no experience with Nios.

 

Until now, I have created my design in Quartus 18.1 using only manually written VHDL, and programmed a pof to the device each time via usb blaster. 

 

Could anybody recommend an approach for somebody like me, and any examples that might help? I have seen the examples that show how to do it via I2C and UART using a Nios implementation, but they are very confusing.

 

Kind regards

AT

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6 Replies
sstrell
Honored Contributor III
359 Views

What exactly are you looking for?  If you don't want to use Nios, you could implement a state machine for control of the config IP.

EricMunYew_C_Intel
Moderator
349 Views

Remote system upgrade allows you to download your pof to flash, you may refer to below for MAX10 RSU and Nios is required.  

https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/an741-remote-system-upgrade-for-max-10...

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an741.pdf


jozephka99
New Contributor II
344 Views

NIOS is NOT required for RSU implementation on MAX10s. You mislead people to the already known topics or examples. I struggled so much at RSU implementation with only fpga logic and it finally I made it. Intel's documentation about it just a couple of lines and it is awful.

 

For RSU implementation on fpga side you must have to 2 basic IPs: On-Chip Flash IP core (user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_ufm.pdf) and Dual Configuration IP core (user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf...

 

The flash memory of max 10 splits into parts relative to your configuration mode. When applying RSU you have to select "dual compressed image". If you do that flash memory splits into 3 section that are CFM0, CFM1 and UFM. You must choose read-write in IP's settings for RSU. CFMs stand as "Configuration Flash Memory" and they holds the fpga's configuration image. UFM stand as "User Flash Memory" and it holds user memory if there any. All of that flash memories logically high when they are empty and you can't change low bit to high, you can just change high bit to low. So if you wanna rewrite this sections you must clear them before write.

 

After you write the rpd to the relevant CFM section with flash ip core you can set the dual config ip's config sel, config sel overwrite and reconfig settings and your fpga reboots from your upfated program. For this logic you can refer to: (https://community.intel.com/t5/Programmable-Devices/Discrete-RSU-User-Logic/m-p/1269878/highlight/tr...)

atattyman
Beginner
331 Views

Hello,

 

Thank you for the detailed reply and sharing your own hard work. I will read and digest the links and code.

 

AT.

GLees
New Contributor I
314 Views

josephka99 is correct, you do not need Nios to perform RSU,  I will warn you, though, you are on a VERY steep learning curve.  There are no step-by-step instructions for this approach, you'll have to dig through various RSU examples and decided which "pieces" are relevant to your own design.  There are many subtleties to overcome and also bugs to work around.  I made it after  weeks of frustration.  Good luck to you.

EricMunYew_C_Intel
Moderator
307 Views

You can store two images in CFM0 and CFM1,2 for remote system upgrade. The dual configuration IP is required for triggering the reconfiguration, and the flash IP is required to read and write to the CFM flash during remote system upgrade.

You may refer to and modify the reference designs below accordingly.

https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/an741-remote-system-upgrade-for-max-10...

https://fpgacloud.intel.com/devstore/platform/17.1std.1/Standard/i2c-remote-system-update-example/


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