Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

MAX10 RSU

takur
Beginner
257 Views

I have implemented RSU over i2c based on this example:

https://www.intel.com/content/www/us/en/design-example/714746/max-10-i2c-remote-system-update-exampl...

 

It’s been working good with a MAX 10M8SAE. I now changed to a MAX 10M16SAE, and regenerated the IP cores for this model.

 

Configuration mode:

- configuration mode: Dual compressed Images

 

Flash memory:

- sector 1 - 0x00000 – 0x03fff - UFM

- sector 2 - 0x04000 – 0x07fff - UFM

- sector 3 - 0x08000 – 0x2dfff - CFM (Image 2)

- sector 4 - 0x2e000 – 0x49fff - CFM (Image 2)

- NA – NA – CFM (Image1)

 

I understand that when using Dual compressed Images, sector 2 and 3 are merged leading to a generated rpd image size of 270336 bytes (0x42000) and that the RSU flash offsets by multiple of 4 bytes. So for 0x08000 - 0x49fff range, RSU indexing goes from 0x2000 – 0x127ff.

 

Yet I get a “flash error” from bit 4 of PrimaryErrors (reg 0x81) when writing passed flash offset 0x0dfd4 (57300).

 

What am I missing?

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5 Replies
NurAiman_M_Intel
Employee
223 Views

Hi,


Thank you for contacting Intel community.


Please provide the full error message/screenshot. Including the error code.


Regards,

Aiman


takur
Beginner
215 Views

Hi

How I can get error code from this example? Is there any others error registers?

Now I can read from register 0x81. This indicate FlashError (bit2 is 1).

 

`define ADDR_PrimaryErrSts 129 //8'h81

RegFile[`ADDR_PrimaryErrSts][ 2] <= FlashError;

 

Regards,

Tapani

NurAiman_M_Intel
Employee
180 Views

Hi Tapani,


Apologize for the delay in response.


When you change from MAX 10M8SAE to MAX 10M8SAE, is there any other changes that were made for the setting or during configuration?


Regards,

Aiman


takur
Beginner
108 Views

Hi

 

No any other changes. Design works fine, but RSU doesn't work.

NurAiman_M_Intel
Employee
161 Views

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