MAX10 Timing Constraints for a Clock Enable fanout?

[TWell6]

I'm working on a project for a MAX10 FPGA, using a clock enable, ClkEnBuffer, which reduces the clock speed by 4.

I've had a look at a Timing Analyzer example (https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/timinganalyzer/exm-tq-clock-enable.html) and modify that.

set_multicycle_path -to [get_fanouts [get_pins {*|CDR|ClkEnBuffer|q*} ] -through [get_pins -hierarchical *|*ena*]] -end -setup 4

set_multicycle_path -to [get_fanouts [get_pins {*|CDR|ClkEnBuffer|q*} ] -through [get_pins -hierarchical *|*ena*]] -end -hold 1

With the multicycle constraints commented out, Quartus completes with no negative slack. With the constraints active, Quartus completes with lots of timing errors (All of them with excess routing delays) up to 2 * ClkEnBuffer delay (8 * clock).

Could anyone help please?

Quartus: Quartus Prime Lite 19.1.0 Edition

[KhaiChein_Y_Intel]

Hi,

Can you share the design for investigation? What is the edition (Pro/Standard) and version you are using?

Thanks.

Best regards,

KhaiY

[TWell6]

As I put on the original question:

> Quartus: Quartus Prime Lite 19.1.0 Edition

[sstrell · Accepted solution]

Your hold multicycle value should be one less than your setup multicycle, so it should be 3 instead of 1. The example you link to has enable every other cycle which is why 2 and 1 are used there. You need to use 4 and 3 for your enable every 4 cycles. Try that and report back.

#iwork4intel

[TWell6]

Thanks sstrell - It's multicycling.