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foft
Novice
100 Views

MAX10 weak pull-ups and leakage current

I'm seeing significant impact from enabling weak pull-ups on pins other than the one I am using.

The specific case is as follows:

Device 10M02SCU169C8G.

In this design I have C1 and D1 connected together. I saw them pulling up with approximately 160uA when tri-stated. I.e. I see 0.8v on the pin if I use a 5K resistor to pull to ground.

I noticed that if I disable the weak-pull up on C2 then the leakage current on C1/D1 vanishes. Note that in my design C2 is actually an unused pin, the weak pull-up was on by default by the 'as input tri-stated with weak pull-up' option for unused pins.

Is this a known issue, perhaps related to the other half of a differential pair?

 

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4 Replies
AminT_Intel
Employee
83 Views

Hello,

 

This may happen because of leakage current in Max 10 device. There is a detail about tristated I/O pin on page 9 from this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf

 

Thanks.

foft
Novice
79 Views

I saw that, but its talking about +/-10uA. 160uA is a fair bit higher. It does say that the 10uA may be exceeded when using the clamp diodes. In fact that isn't what I see here. I see it happen not with the clamp diodes but the weak pull up on another pin that I'm not using.

AminT_Intel
Employee
55 Views

Hello,

 

May I know which version of Quartus are you using and if you can share you sample design.

 

Thanks.

foft
Novice
40 Views

I've seen this in Quartus lite versions for the last few years, now using v20.1. I'll post the .qar this evening.