MAX10m08 board SDRAM access example

Altera_Forum · ‎09-02-2016

Hi,

I'm a student and new to FPGA design.

I'm trying to access external SDRAM on MAX10M09 board via SDRAM controller. The main idea is to write into a certain address with a certain value and then read it out and display it on led. After each write-read cycle, the value will be increased by 1. Total cycles will be 8 and then reset.

I use one SDRAM Controller to connect DDR SDRAM on board. Then a verilog module(state machine module) to connect with SDRAM controller to apply write-read action. Finally a PLL to give clock signals.

The state machine works like; null stage -> write stage -> write-wait stage -> read stage -> read-wait stage. Then it will go back to write stage if not reset.

There are two signals sent from SDRAM which are WaitRequest and ReadValid. The WaitRequest indicates if the SDRAM is busy or not. When the ReadValid signal is 1, we can read the output of SDRAM.

So far, I just use LED to follow the stage flow. My problem is the state machine is always stuck at read-wait stage because it couldn't get DataValid signal...

I upload the example. Does anyone can kindly help to check it?

Thank you so much!

Rocky

Altera_Forum · ‎09-02-2016

Sorry, wrong file type was selected. This is the right zip file.

Thanks

Altera_Forum · ‎10-20-2016

Finally, I got it.

Several mistakes were made:

1. I didn't connect clock pin to DDR SDRAM. That pin was not created by 'SDRAM controller' module which was wired.... So I created one output pin on my top design to supply clock input to SDRAM.

2. The default reset signal in 'SDRAM controller' module was opposite of my top design. So everytime my top module was turned on but the SDRAM controller was off.

Thanks