Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

MAXII Code

Firefighter
Beginner
590 Views

Hi Intel,

I am reading some reference code for MAXII CPLD.  It is below. I do not understand what it is doing. Any one can help?

maxii_io
d_bit_13(.datain ( sck), //serial_clk_out
.oe (DC2026_DETECT), //DC2026_DETECT=1 SCK_33=sck & gated_sck, DC_2026_DETECT=0 SCK_33=HiZ
.padio (SCK_33), //pin to SCK of LTC2380-24
.combout (B13)); //
defparam d_bit_13.operation_mode = "bidir";

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sstrell
Honored Contributor III
578 Views

This is an instantiation of a module named max_ii_io.  datain, oe, padio, and combout are the I/O of the module and sclk, DC2026_DETECT, SCK_33, and B13 are what they connect to in the current level of the design.  The defparam is sending a parameter value of "bidir" to a parameter named operation_mode in the instantiated module.

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Firefighter
Beginner
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Hi Sstrell,

 

Thanks for your reply.

Is max_ii_io module a library or something that Quartus integrated, just like DFF? I tried to search it in the project verilog code, but could not find it. I also search it in the MAXII book. No luck.

 

Cheers

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sstrell
Honored Contributor III
531 Views

Not a clue.  This is just standard Verilog code.  I don't know where you got it from or where you saw it.

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Nurina
Employee
516 Views

Hi,


Did the above reply help?


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Firefighter
Beginner
510 Views

Hi, Nurina and SStrell,

Thanks for help. It can be closed now.

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Nurina
Employee
503 Views

Glad your problem has been solved. I shall close the case now.

Regards,
Nurina

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