MAXII to MAX5 CPLD foot print compatability

[KrishnamRaju]

Dear Team

We are chaning MAX CPLD II EPM2210F256C5N with MAX V CPLD 5M2210ZF256I5N .

1. Are both CLPDs foot print compatiable?

2. In my old design for MAXII VCCINT 3.3V is there and Now I am changing it to 1.8V as MAXV requires. Same symbol and foot print of CPLD II is used. Is it ok?

With Regadrs

Krishnam Raju M

[FvM]

Hi,
the devices are basically  pin-compatible. I suggest to check the signal assignments by importing the MAX II pin assignments to MAX V design and check dedicated power, ground and JTAG pins separately.

[NazrulNaim_Intel]

Hello,

Sorry for the delay. As user 'FvM' have replied. The reply can be accepted which is the devices are pin compatibility and need to check the signal assignments by importing the MAX II pin assignments to MAX V design. Do let me know if I can assist you further.

Best regards,

Nazrul Naim

[KrishnamRaju]

Dear Naim

I found a T6 pin which is ground in MAX V is I/O in MAX II. 

Can you please look at this and the reason for this difference.

With Regards

Krishnam Raju M

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[FvM]

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@KrishnamRaju wrote:

I found a T6 pin which is ground in MAX V is I/O in MAX II. 

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So you found that the devices are not 100 % pin-compatible.  I guess, there's a reason why T6 is now assigned to ground, but knowing it won't help you much. If T6 is used as IO in your MAX II design, you need to modify the PCB.

[NazrulNaim_Intel]

Hi Krishnam Raju M,

Sorry for the delay. For your information since MAX II and MAX V are both different device which you have stated T6 pin which is ground in MAX V is I/O in MAX II. Thats why the pin assignment is different from each other.

For more information you can access these links for the device handbook for MAX II and MAX V

Link MAX II: https://cdrdv2.intel.com/v1/dl/getContent/655094?explicitVersion=true&fileName=max2_mii5v1.pdf
Link MAX V:  https://cdrdv2.intel.com/v1/dl/getContent/654928?explicitVersion=true&fileName=max5_handbook.pdf

Hope that helps.

Best regards,

Nazrul Naim

[KrishnamRaju]

Dear Naim

Thank you.

1. I had already mounted MAX-V in place of MAX-II. 

2. I found only T6 as the difference which was used as GPIO in my design. This GPIO is not crucial for my design. Can I gohead with testing?

Will it create any problem?

With Regards

Krishnam Raju M

[FvM]

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@KrishnamRaju wrote:

 I found only T6 as the difference which was used as GPIO in my design. This GPIO is not crucial for my design. Can I gohead with testing?

Hi,
good if you can get along without usingT6 as GPIO. Preferably you'll connect the pin to ground, but I guess MAX V will work even if you leave it floating.

Regards
Frank

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[NazrulNaim_Intel]

Hello,

As per user 'FvM' have replied. The answer can be accepted which is you will need to connect the Pin T6 to the ground and it will not create any problem.

Hope that helps.

Best regards,

Nazrul Naim

[NazrulNaim_Intel]

Hello,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Best regards,

Nazrul Naim

[KrishnamRaju]

Dear Naim

Please help us on below poits,

1. Before programming the CPLD MAX V, What are the default states of all I/Os.

Initiall after power up all I/Os(Before programming the CPLD) are driving some logic to processor beacuse of which I am facing some issue.

2. I want to keep all un used pins as input with high impoedence after programming the CPLD. How to make this setting in Quartus tool.

With Regards

Krishnam Raju M

[FvM · Accepted solution]

Hi,
It's all described in device handbook and datasheet.

GPIO have weak pull-up resistors to respective VCCIO until user mode becomes active. State of unused pins can be globally selected in Quartus device and pin options.

"Reserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up."

Personally, I won't choose high-Z without pull-up if there are any unconnected GPIO pins because floating inputs can involve additional device current consumption.

Regards
Frank 

[KrishnamRaju]

Dear Frank

Thank you

[KrishnamRaju]

Dear Frank

We want to Keep MAX-V CPLD without giving Core power and one Bank I/O power(Bank 3 1V8) (As we are not using this). But due to our design limitation we are giving power to other 3 I/O banks.  Is it ok?

Some of the I/os(Not powered) are connected to the Processor . In this condition our power circuit is beahaving weirdly.

Is it ok to keep CPLD in this condition or better to remove this IC from the board?

With Regards

Krishnam Raju M

[FvM]

Hi Krishnam,
I'd rely on MAX V hot socketing specifications in this regard:

■ The device can be driven before and during power up or power down without
damaging the device.
■ I/O pins remain tri-stated during power up. The device does not drive out before
or during power up, thereby affecting other operating buses.
■ Signal pins do not drive the VCCIO or VCCINT power supplies. External input signals
to the device I/O pins do not power the device VCCIO or VCCINT power supplies
using internal paths. This is true if the VCCINT and VCCIO power supplies are held at
GND.

Entry into user mode is gated by whether all the VCCIO banks are powered with
sufficient operating voltage. If VCCINT and VCCIO are powered simultaneously, the
device enters user mode within the tCONFIG specifications. If VCCIO is powered more
than tCONFIG after VCCINT, the device does not enter user mode until 2 µs after all VCCIO
banks are powered.

Not sure where you see weird behaviour. According to device handbook, the described operation conditions are acceptable.

[KrishnamRaju]

Dear Frank

Thank you for your valuable reply.

We are giving only I/O banks power and not providing core power. What is the state of I/Os in this case?

Is It ok to keep MAX V CPLD in this state?

We are suspecting some assembly issue of this device and want to keep this device out of picture.

Thank you