What is the minimum number of logic elements I should expect the Quartus II (v14.1.0) synthesis/fitter to compile for a MAXV part needing 16x16 RAM (256 bits)? I've created/built several Verilog projects and each is giving a different result. I understand that a bug may exist and/or each particular Verilog source may route and place things differently, but not knowing what minimum number of logic elements I should expect - I just don't know if a bug exists - and or if I should bother optimizing the synthesis/fitter. One of my tests included just the Altera single_port_ram.v with the RAM: 1-Port Megafunction included. So, removing all the source code issues and particulars about build optimization, I'm just looking for the minimum number of logic elements needed to support a 16x16 (256 bits) RAM on the MAXV part.
