Hello! I'm trying to implement MIPI D-PHY transmitter on MAX 10 Dual supply FPGA.
In Application Note 754 it is written that:
High-speed mode — A differential buffer is used to transmit signals.
Low-power mode — A differential buffer is configured as input mode to act as tri-stated output.
and in high speed mode IO standard is Differential HSTL-18.
In example they used an emulated LVDS, so they could use tristate buffers for each positive and negative LVDS line. But i'm concerned about maximum possible speed with that solution, because i need at least 600 Mbps.
So there are my questions:
Hello, thank you for your answer.
About OE. As written in AN745 to implement MIPI D-PHY with passive resistor network using Intel FPGA one needs to connect two single ended lines through resistors with differential lines. So when Lane in Low Power state, on both of these single ended lines will be a high level signal around 1.2V than will come right to lvds buffer. So i'm afraid that if this lvds buffer does not have anything like output enable signal, that will drive it's lines to high impedance state, it will disturb Low Power state or worse like burn down the internal circuits.
So my question was, in another words, how can i create D-PHY physics with passive resistor network? What kind of IO standard do i need to assign to my output pins and whether high speed pins should be tristated?