- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I am trying to load my program to a Block RAM using Data2mem, after the bitfile is generated. Here are the steps:
- I have generated a BLOCK RAM as single port ROM with 32 bit-width and 16384 bit-depth.
- Then translated the design without any BMM file and looked at the PlanAhead tool to see which BRAM are used and which ramloop is assigned. There are 15 ramloop lines. There are 14 PRIM36 primitives and 1 PRIM18 primitive as shown below:
- I wrote the following .BMM file for address the ROM from 0x0000 to 0xFFFF. and add it to the xilinx project.
- But when I tried to compile it again it gives me the error:
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You realize this is a forum for Altera devices.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page