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Hi there,
I use Max 10 10M04DAU324 Series FPGA in our design. Only I konw that IO status keeps tri-state with internal weak pull-high when CFM to SRAM(config mode) as attachment picture showed "2". I wonder the IO status keeps tri-state OR remain high when JTAG programming status as attachment picture showed "1". Is there have any official doc can prove IO status at JTAG programming on Max 10, thanks.Link Copied
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--- Quote Start --- In a normal ISP operation, to update the internal flash with a new design image, the device exits from user mode and all I/O pins remain tri-stated. --- Quote End --- Whenever the device is not in user mode all I/O are tri-stated. This includes when the device is being configure via JTAG. See the 'max 10 fpga configuration user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_config.pdf)'. Cheers, Alex
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Hi Alex,
'MAX 10 FPGA Configuration User Guide' doen't specified IO status when jtag programming, I do some experiment at MAX® 10 FPGA Evaluation Kit with checking set IO remaing weak-pull high piror User Mode(default is pull high), and have strange things happend, I wonder that is Quartus 16.1 tool's bug. Thanks.- Mark as New
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Are you using the ISP Clamp feature?
Cheers, Alex- Mark as New
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Hi Alex,
No, But I know that ISP Clamp is workable. Discussed with Altera AE, they still test on this problem. Thanks.
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