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Hello, I have a problem with the max 10. I have programmed it in the flash memory the code, but I am not able to start the FPGA. I leave you a part of the schematic of the configuration pins.
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Hello,
Fix it, It was problem of the quartus when it created the file. I don't know why...
Thanks
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Hi,
Thank you for contacting Intel community.
- Max 10 does not need to power cycle.
- Try to check your design: pin connection, IP address, etc..
- Try a simple design such as LED blinking and see if the LED is blinking or not. If yes, that means there is no problem with your Max 10.
Let me know your concern.
Thanks.
Regards,
Aiman
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Below are the link:
Max 10 configuration userguide:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf
Max 10 pin connection guidelines:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/PCG-01018.pdf
Regards,
Aiman
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Hi, it is not starting with a proven design? After programming and or at power up?
Try a simple design can be tested on board, IE an LED connected to JTAGEN, generate and load as SOF without programming Flash.
Test Config_done and nConfig level, if not High test all other configuration input for high level.
In case of failure try add 4 more resistor + 1 cap:
10 KOhm pullup to CRC err (known) TDI TMS (less importance)
1 KOhm pullDOWN to TCLK (Possible caveat)
10-100 nF cap from CLR_n to ground
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I cannot modify message...
About CRC Error, I checked two of my design, is connected to logic without pullup.
Please try verify flash and tell us about what is on console.
From what I remember I got troubled by some pin driving nConfig, ConfigDone, nStatus, are these pin free on your design or shared to?
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Hello,
Sorry for the delay. I have had not enough time to proof it. This night will test it and comment you.
THank you
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Hello,
Fix it, It was problem of the quartus when it created the file. I don't know why...
Thanks
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