- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Does Max V CPLD has inbuilt ADC or DAC. If yes then how can i interface it with CPLD. :)
Link Copied
5 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It doesn't have an ADC or DAC.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Does Max V CPLD has inbuilt ADC or DAC. If yes then how can i interface it with CPLD. :) --- Quote End --- As Leon points out, Altera CPLDs and FPGAs do not have ADCs and DACs. You can however create a DAC using a PWM waveform and low pass filter (Altera have an app note on this), or an ADC using an LVDS receiver (Lattice have an app note on this). There are plenty of SPI ADCs and DACs from multiple vendors. They are very simple to interface to. I can post examples. What kind of speed/update-rate were you looking for? Cheers, Dave
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello!
I bought last week max V cpld and has installed Board Test System to go through a design example for learning how it works. I wonder where I can find manuals of these design examples, i.e how/where I begin to start using and learning understand the design example. Thanks- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I know this is an old posts.
You can however create a DAC using a PWM waveform and low pass filter (Altera have an app note on this), or an ADC using an LVDS receiver (Lattice have an app note on this). Would you point me to those links? Thanks- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Would you point me to those links? --- Quote End --- Browse the Altera app notes: https://www.altera.com/support/literature/lit-an.html Here's the PWM app note https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an501.pdf https://www.altera.com/content/dam/altera-www/global/en_us/others/literature/an/an501_design_example.zip Do the same on the Lattice site. The app note I was recalling is probably this one on Sigma-Delta ADCs: http://www.latticesemi.com/en/products/designsoftwareandip/intellectualproperty/referencedesigns/referencedesign03/simplesigmadeltaadc.aspx This has links to a PDF and source code. Cheers, Dave
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page