Max V Development KIT 10MHz external clock pin map ?

[Altera_Forum]

Hi 

I'm new to CPLD as well as VHDL. I am going to buy a Max V Developement KIT, and my first project is bulding a time multiplexer. I need to use the 10MHz clock as an input signal for this time multiplexer, however I could not find the pin map of this external clock (which pin on the CPLD Max V corresponds to this 10MHz external clock ?). As in the link below: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_maxv_cpld_dev_board.pdf It shows that the external clock is pin J1 board reference. But it does not say what is the cpld Max V pin reference of this clock.  Where can i find this information? Thanks alot. Bien

[Altera_Forum]

This clock goes in to pin H5 in bank 1. There doesn't seem to be a reference to this in the user guide. Refer to the board's schematic. 

 Cheers, Alex