Max10 - Are there internal weak pull-ups on the pins during flash load.

[GLB]

I am working on a new design for the Max 10 10M25SCE144A7G FPGA. I would like to confirm that the device implements an internal weak pull-up on all tri-state pins during flash load of the FPGA code.

This has been my experience on other Altera FPGA’s but I can’t seem to find conformation in the datasheets for the Max 10 family. I know you can configure the use of an internal weak pull-up after load but I need to be sure the weak pull-ups are applied prior to load to be sure I know the initial state of the pins connected to my external logic during power-up.

[a_x_h_75]

Yes, there are. Refer to table 17 in the MAX 10 datasheet.

"Value of I/O pin (dedicated and dual-purpose) pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled"

Cheers,

Alex

[Rahul_S_Intel1]

Hi , Kindly find the flow chart for the I/O states before ,during and after configuration Page no:28 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf