I am working on a new design for the Max 10 10M25SCE144A7G FPGA. I would like to confirm that the device implements an internal weak pull-up on all tri-state pins during flash load of the FPGA code.
This has been my experience on other Altera FPGA’s but I can’t seem to find conformation in the datasheets for the Max 10 family. I know you can configure the use of an internal weak pull-up after load but I need to be sure the weak pull-ups are applied prior to load to be sure I know the initial state of the pins connected to my external logic during power-up.
Yes, there are. Refer to table 17 in the MAX 10 datasheet.
"Value of I/O pin (dedicated and dual-purpose) pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled"