Max10 PLL input clock switchover example?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Max10 PLL input clock switchover example?

998 Views

I read max10 datasheet and it says that its PLLs support input clock switchover. I tried to used altpll IP-core in qsys(Platform design) to configure this feature but the "clock switchover"-Tab is always inactive and I couldn't find the way to activate it.

Is there any example for using PLL input clockswitchover in Max10?

Thanks alot.

Bien

20 KB

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.