I am having problems with Max10 configuration. After I successfully program the fpga the conf_done pins stays low. Actually the conf_done pin goes high for a moment at the beginning of jtag programming and again for a moment at the end of programming cycle. Than it stays low and the design doesn't work.
I have pull-up resistor on nStatus, Conf_Done, nConfig.
I have pull-down on ConfigSel, JTAG-TCK and JTAG-TMS. I also tried pull up on TMS, but no change.
The rest is floating. I thought this is no problem, because I don't use the Enable Device-Wide reset (DevCLRn) and Device Wide outpout enable (DEV_OE) options.
Does anybody have an idea where could be the problem. I have no idea what else to try?
Let me answer to myself
Thank you for let's Intel FPGA community here know the solution/answer.
Yes, some time the unstable power rail might cause an issue to FPGA pins. And worst part is when the pin is the Configuration pins(cause failure to configuration)