Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19341 Discussions

Max10 conf_done stays low

fogl
Novice
491 Views

Hello everybody,

I am having problems with Max10 configuration. After I successfully program the fpga the conf_done pins stays low. Actually the conf_done pin goes high for a moment at the beginning of jtag programming and again for a moment at the end of programming cycle. Than it stays low and the design doesn't work.

I have pull-up resistor on  nStatus, Conf_Done, nConfig.

I have pull-down on ConfigSel, JTAG-TCK and JTAG-TMS. I also tried pull up on TMS, but no change.

The rest is floating. I thought this is no problem, because I don't use the Enable Device-Wide reset (DevCLRn) and Device Wide outpout enable (DEV_OE) options.

 

Does anybody have an idea where could be the problem. I have no idea what else to try?

Regards

Klemen

0 Kudos
3 Replies
fogl
Novice
482 Views

Now I also set the DevCLRn and DEV_OE to tri-state input with a weak pull-up. But still the same.

I have got no more ideas.

Regards

fogl
Novice
463 Views

Hello,

Let me answer to myself The reason for such behavior was power supply failure. The fpga was configured correctly, but afterwards it turned on an electrical load (which should be turned on with a soft start) that caused a voltage drop on 3.3V power rail and reset of the fpga.

Regards

Klemen

ShafiqY_Intel
Employee
457 Views

Hi fogl,

 

Thank you for let's Intel FPGA community here know the solution/answer.

 

Yes, some time the unstable power rail might cause an issue to FPGA pins. And worst part is when the pin is the Configuration pins(cause failure to configuration)

 

Regards,

Matt

 

Reply