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Hi :
From the Altera agilex 5 MIPI D-Phy IP User Guide,
We Know that We can use MIPI Standard IO (HS/LP Compatable IO) By Using Altera MIPI
DPhy IP.
I Want to ask If we can use MIPI Standard IO (HS/LP Compatable IO) Without Using
Altera MIPI DPhy IP ( Maybe we can Tie the HS/LP Control Signals to the MIPI Standard IO)
If We can not do this kind of things,
May I ask the reason Why we can not use MIPI Standard IO (HS/LP Compatable IO) Without
Using Altera MIPI DPhy IP.
If We Use Altera MIPI DPhy IP, the Data/Clk Lane IO Pin Locations is dedicated by your user
Guide, So agilex 5 FPGA Do actually have MIPI Standard IO (HS/LP Compatable IO),
is the answer Correct !?.....
If agilex 5 FPGA Do actually have MIPI Standard IO (HS/LP Compatable IO), Why we can
not use this kind of IO and Tie the HS/LP Control Signals to the MIPI Standard IO, directly !?...
thanks for your answer.
Sincerely regards~
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Thank you for reaching out to Altera Community Forum. Our SME is currently out of the office and will be returning on 3-Jan-2025. We apologize for any inconvenience this may cause. In the interim, we welcome the community to contribute with any questions, and we’ll strive to offer support whenever possible.
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Hi ,
Please accept my late response.
So agilex 5 FPGA Do actually have MIPI Standard IO (HS/LP Compatable IO), is the answer Correct !?.....
>> following user guide under https://cdrdv2-public.intel.com/834802/ug-817561-834802.pdf
>> There is a block who handles the external incoming data deserialization with its clocking for both HS and LP modes
Regards,
Wincent
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Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
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Hi
We have not hear from you and this Case is idling. It is not recommended to idle for too long.
Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause
Hence, This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Altera experts.
Otherwise, the community users will continue to help you on this thread. Thank you
If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
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Hi Wincent :
Recently, I am on my travel vacation in Japan.
So, I Can't reply your message quickly.
thanks for your reply.
From your answer,
It seems that the agilex5 FPGA MIPI IO can not use alone (must use with Agilex5 MIPI D_Phy)
because "There is a block who handles the external incoming data deserialization
with its clocking for both HS and LP modes"
Is my understanding about this answer correct !?...
thank you~

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