Mega Function RAM I/O Data Bus

[Altera_Forum]

I'm trying to implement a memory buffer between microcontroller and EP3C16 . I'm using Mega function to generate the RAM memory. The problem is that it generates separate input and output data bus. I want to make single and bi-directional data bus to comply with the microcontroller and save pins. Any ideas?

[Altera_Forum]

The FPGA's internal RAM can only be generated with separate input and output buses. You can't generate one with a bi-directional data bus. 

 You'll have to wrap your RAM with some logic that determines when to: a) read the RAM's output bus and drive it to the Micro and b) when to tri-state the FPGA's pins and drive the data received from the Micro into the RAM via the input bus.  Cheers, Alex