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When creating a mega function, does it make any difference if you select AHDL, VHDL or Verilog VHDL for the output file? Does it all get mapped to the same Logic Elements in the same way regardless?
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That's pretty much correct.
The Modelsim Altera Starter simulator only supports VHDL or Verilog (not both at the same time), so if you want to simulate your system, then you need to select a specific language.
If you code in VHDL or Verilog, then you will often code lpm_counter and other components directly in your code rather than going through the MegaWizard tool.
Cheers,
Dave
