Migration from EP3C80F780 to EP3C120F780

[Altera_Forum]

Good afternoon, 

 I am dealing (maybe) with a migration issue. I changed my quartus II project from an EP3C80F780 to an EP3C120F780 device. I did not remove all the pins assignments because the PCB that we are using is developed in order to be used with both type of FPGAs, and that the footprint of both is exactly the same. The project I am developing, uses the FPGA to drive an analog board, and also to compute some models (for example an electrical generator) regarding that board.  Globally the system works properly, but if I look to some of the results, I see slightly changes in the models behavior. This problem could be related to the PCB itself, but in order to be sure that it is not related to migration I would need the answer for 3 questions :  - Can I keep the same pin assignments than for the EP3C80F780 without any troubles ?  - Could it be possible that the migration from one device to the other leads to some changes in hardware computation such as adder or multiplier that would operate differently ? - More generally, could I meet any kind of problems regarding this way of migration ?  I also need to mention that at the beginning of the project I did not add the EP3C120F780 FPGA as migration device, because I did not know that I would have to use it in the future.  Thank you for your assistance

[Altera_Forum]

Migration is one pet peeve of miine with Altera. They need to provide a "Migration" pinout file: 

 If you look at the "Maximum User IO's in table 3 of the overview page you can see the potential issues:  http://www.altera.com/devices/fpga/cyclone3/overview/cy3-overview.html  The 780 package has migration capability between the C40, C55, C80 and C120. However, the maximum number of io's change between the family members.  The C40 has 545, C55 has 377 the C80 has 429 and the C120 has 531. So to be truely migratable, you need to limit the design to no more than 377 IO's.  If you look closely at the pinout's you find that on some of the devices certain pins are NC, others are VCCIO's others are GND. depending on the family member.  So you apparently have made it passed the first step, in the design compiled with the existing pinout targeting the larger device. However, you need to also very that the Layout is "Truely" compatible for the larger device, in that all VCCIO's and GND's are connected as such (they may have been IO's on the C80).  To truly validate this, I take the spreadsheet for all family members in a particular package, and cross reference the pinouts, to vaildate all configuration pins, and all VREF's, clocks, VCC's GND's etc for every pin. Making a "Migration" pinout spreadsheet, that I then use to guild the layout  I have requested ALTERA produce this time and time again, but so far no one is listening. They say the "Migration" option in the tool will tell you. But it won't tell you that the IO's you aren't using in this device are VCCIO or GND in the next device up.  And most of the time, you are defining the pinout before you have a design done, because you need the board, so it's nice to know the pins your are selecting are "ALWAYS" good, and not happened to be good because the logic behind them got optimized out, because it isn't there yet.   Grumble...  On your other question. If the pinout is good and the board power is good to support the larger device, your timing is probably different.  Make sure your timing reports are clean. It could be that's your problem.  Pete

[Altera_Forum]

if you turn on migration and generate a .pin file in Quartus, it should show the pins that are user I/O in smaller devices and power in larger devices as being power pins