Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
19493 Discussions

Minimum hold time for input pins on MAX10

Altera_Forum
Honored Contributor II
780 Views

How do I find the minimum hold time for input pins on MAX10? 

 

I want to use a discrete high-speed comparator combined with fast event capture in the FPGA to implement a simple ADC, and may have to latch the comparator. In either case, I need to know the minimum hold time for the MAX10 inputs.
0 Kudos
0 Replies
Reply