Minimum hold time for input pins on MAX10

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Minimum hold time for input pins on MAX10

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How do I find the minimum hold time for input pins on MAX10?

I want to use a discrete high-speed comparator combined with fast event capture in the FPGA to implement a simple ADC, and may have to latch the comparator. In either case, I need to know the minimum hold time for the MAX10 inputs.

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