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Altera_Forum
Honored Contributor I
1,763 Views

Minimum pulse width error

Hi, I am geting a minimum pulse width error when I am trying to send a clock signal throw my fpga.  

 

verilog code:  

module top (  

input CLK_125, 

output TX_CLK 

); 

 

always TX_CLK = CLK_125; 

endmodule 

 

.sdc file:  

create_clock -name clk125 -period 8.000 [get_ports {CLK_125}] 

create_generated_clock -name gtx_clk -source [get_ports {CLK_125}] [get_ports {TX_CLK}] 

derive_clock_uncertainty 

 

timequest report: 

slow 1200mV 100C Model : 

slack: -5.445 , actual widht: 8.00 , required width: 13.445 , Type: Port Rate  

fast 1200mV -40C Model: 

slack: -12.00 , actual widht: 8.00 , required width: 20.00 , Type: Port Rate 

 

in Pin Planer:  

CLK_125 has location PIN26 and i/o standard 3.3V LVCMOS with current strength 2mA 

TX_CLK has location PIN30 and i/o standard 3.3V LVCMOS with current strength 2mA 

 

I am using a Max 10 fpga with speed rating I7 (10M50SC144I7G) as, if i have undrstood the datasheet corectly, has a ouput data rate of 310 MHz.  

 

Why does timequest report an error?
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4 Replies
Altera_Forum
Honored Contributor I
184 Views

Increase the drive strength on TX_CLK to maximum. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
184 Views

 

--- Quote Start ---  

Increase the drive strength on TX_CLK to maximum. 

 

Cheers, 

Alex 

--- Quote End ---  

 

 

Changed current strenght from "2mA(default)" to "Maximum Current". It did not change anything.  

But, thanks for the answer
Altera_Forum
Honored Contributor I
184 Views

Your voltage to your device is e.g.  

1) 3.3V to +ve pin and gnd(0V) to -ve pin, creating 3.3V potential difference or  

2) 2.6V to +ve pin and -0.7V to -ve pin, creating 3.3v potential difference too.  

Case 1) Your will need go to datasheet single supply which is 100Mhz, whenever your -ve is ground, it is known as single supply 

2) You get 310Mhz for putting 1.65V and -1.65V(potential diff 3.3V), meanwhile getting less and less Mhz>>e.g. 2V and -1.3V(potential diff also 3.3V) but get 240Mhz for example. Dual supply method whenever not grounding the -ve pin 

 

It work like swinging voltage, and you can read about the working principle of swinging voltage. 

 

Also, changing the 2mA means you are doing current source, LED is sourcing current because forward voltage of LED=Vf from fundamentals of LED is a fixed voltage at the PN junction. Whereas for motors/processors, you are only playing with the voltage, means source voltage, changing voltage at +ve and -ve there you will get difference ranging Mhz as I explain on top. This is how datasheet have min value, typical value, and maximum value. 

 

I assume you are grounding your -ve pin, which is 0V, and so the minimum is 10Mhz at mode x1.
Altera_Forum
Honored Contributor I
184 Views

Minimum pulse width checks are done to ensure that width of the clock signal is wide enough for the cell’s internal operations to complete. i.e. to get a stable output you need to ensure that the clock signal at the clock pin of the flop is at least of a certain ‘minimum’ width.  

 

You get this error from TimeQuest due to the fact that the required time (13ns)is greater than the actual time(8ns). You need to constrain the clock pins with the minimum pulse width constraint. For the clock signal to be passed successfully, the Actual time should be greater than the required time so that you meet the minimum pulse width requirements. 

 

set_min_pulse_width -high 4.0 [all_clocks] 

set_min_pulse_width -low 4.0 [all_clocks]
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