I have a PCIe system. RC is Terasic CV GX board, EP is Altera CV GT board. I write test data (inc counter value) from RC NiosII through simple DMA controller to RC Txs port, data go out EP BAR0 port and is written to EP onchip ram. Then I read from RC NiosII through RC Txs -> EP BAR0 the data from EP RAM. This memory check works fine, I check the written data and read back data it in RC NiosII. 1. When I change the destination address from EP onchip RAM to EP PCIe TXs port (send data not to EP RAM from EP BAR but directly to EP TXs Port), I see that data on EP BAR0 AVL master port are not the same, one word may be missing in burst packet (see attachment). 2. During configuration I set RC ATT and EP BAR with the same value. What is the purpose of the RC BAR and EP ATT? I do nothing with them and the system works (to say nothing of missing words) Thanks in advance!