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Mixed I/O pin standards and VCCIO

Twincreeks
Beginner
1,154 Views

I am using a Cyclone 10 GX device. Can I use a 1.2 V LVCMOS output pin in an I/O bank with VCCIO of 1.8 V? In the same I/O bank, can I also use LVDS input pins and differential SSTL-12 output pins with on-chip calibration? I read the I/O handbooks, but I cannot find the answer.  

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AminT_Intel
Employee
1,093 Views

Hello,

 

Yes there is. You can use Chip/Pin Planner under Assignment tab on your Quartus. 

This is the tutorial video that you can refer to: https://www.youtube.com/watch?v=Bt-yDRReKZw

We have a few tutorial videos that you can refer to on our Youtube channel: Intel FPGA 

 

Hope this helps.

Amin.

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AminT_Intel
Employee
1,135 Views

Hello,

 

You can only use 1.2 V Vccio for input and output of 1.2 V LVCMOS.

 

The Intel Cyclone 10 GX devices support OCT in all FPGA I/O banks. For the 3 V I/Os,
the I/Os support only OCT without calibration. OCT with calibration is available for LVDS I/O and so as Differential SSTL-12. 

You may look for further details on your device GPIO document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf

 

Thank you,

Amin

 

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Twincreeks
Beginner
1,131 Views

Thank Amin for your reply. 

Can you clarify the following general rule? Per "Intel Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook" (C10GX51003 | 2020.09.25) Page 91, Table 34, 

1) for a 1.2 V LVCMOS output pin, must VCCIO be 1.2 V?  

2) for a differential SSTL-12 output pin, must VCCIO be 1.2 V? 

3) for an LVDS output pin, , must VCCIO be 1.8 V? 

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AminT_Intel
Employee
1,119 Views

Hello,

 

1) for a 1.2 V LVCMOS output pin, must VCCIO be 1.2 V?  

Yes.

 

2) for a differential SSTL-12 output pin, must VCCIO be 1.2 V? 

Yes for the Vccio output pin.

 

3) for an LVDS output pin, , must VCCIO be 1.8 V? 

LVDS I/O bank supports differential and single-ended I/O standards up to 1.8 V.

 

Thank you.

 

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Twincreeks
Beginner
1,116 Views

Thank you for your further clarification. Your answer to my third question is still ambiguous. LVDS has two meanings in the handbook, the general LVDS /IO bank (comparing with the 3 V I/O bank) and the specific LVDS I/O standard (comparing with SSTL-12). What I am asking is the specific LVDS I/O standard, while your answer is about the I/O bank. For an output pin in the LVDS I/O standard, must VCCIO be 1.8 V? 

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AminT_Intel
Employee
1,113 Views

Hello,

 

Yes you need Vccio 1.8 V output for. LVDS I/O Standard.

 

Thank you.

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Twincreeks
Beginner
1,110 Views

Thank you for your confirmation. 

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Twincreeks
Beginner
1,102 Views

Is there any way to assign in the Quartus software what the VCCIO of a specific I/O bank is, in addition to the I/O standard of a specific pin?  

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AminT_Intel
Employee
1,094 Views

Hello,

 

Yes there is. You can use Chip/Pin Planner under Assignment tab on your Quartus. 

This is the tutorial video that you can refer to: https://www.youtube.com/watch?v=Bt-yDRReKZw

We have a few tutorial videos that you can refer to on our Youtube channel: Intel FPGA 

 

Hope this helps.

Amin.

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