Must I connect CK,CK# to dedicated PLL output pins when using DDR2 soft controller?

[Altera_Forum]

I'm using the DDR2 soft controller in cyclone V. I want to know how should I connect the CK, CK# pins? Do I need to connect them to dedicated PLL output pin pairs(only 3 pairs available in my FPGA,5CEBA2F23C8)? or I can connect them to any differential output pin pairs?

[Altera_Forum]

I was about to recommend you connect them to PLL output pins as this could offer you flexibility - the clock you drive out of these pins need not necessarily come from the PLL. 

 However, having just check the schematics for Altera's Cylone V E development kit, they drive the clock out of a standard diff output pair. Yes, this board uses 2x DDR3 devices but that practice will equally apply for DDR2.  Whatever you chose to do I strongly recommend you use Altera's tools (Quartus etc.) to validate your pinout before having your board manufactured. It's free to use (for Cyclone V anyway) and, although it'll cost you a little effort (you'll have to put a small FPGA design together with your DDR2 controller), it'll tell you whether it's happy with your chosen pinout.  Cheers, Alex