My verilog code work in stimulation but not working in hardware

[MooQZ]

This is my assignment that required to design a traffic light with delays, display countdown with 7 segment display. My verilog code is working in stimulus using Modelsim but not working in Hardware(Cyclone II EP2C35F672C6N), I can't find where is the problem causing this.
Every component have tested individually in modelsim and get the ideal output.

Troubleshooting for hardware:

1. Output the is5, is0 signal using led - no problem, its working it can detect 5 and 0
2. Output sel, load and countstrt signal - stuck at countstrt = 1, seems like stuck at Sd1
3. After changing the counter code the counter count from 9 when it reach 5 OUTH=100, and OUTC = 000 which is wrong and stuck at 00 for not moving to another state
4. The counters are working but the fsm seems like not working properly. It is not FPGA board problem. I try on 2 different boards and get the same output.
5. The clk are working cuz the one hot counter does count correctly(clk_0.5s) and another counter countdown in DP1 is working too( -1 every second)
6. After display the state using LED, I found that the state stuck at S1 (S0 -> S1 -> Sd1(reach 5 OUTH=100, and OUTC = 000) -> S1)
7. I had tried to test my fsm code using the fpga board and it works Output virtualize table

[FvM · Accepted solution]

Hi,

project source files are incomplete, e.g. many missing modules, e.g. max21_param, counter, comparator_equal, buffer, thus can't check the design.

Notice that you don't have a testbench for top level design, without simulating the full design succesfully you can't claim that it simulates o.k.

A possible source of hardware-to-simulation mismatch is the use of ripple clocks clk_0_5s and clk 1s that may cause timing failure. Better use one system clock (50 MHz clock) together with low frequency clock enable pulses. 

[MooQZ]

Thank you I have solved my problem by changing another clk_div. I didn't upload the other sources file and test bench code cuz here got 10 file upload limit, sorry for the incomplete of source file.

[FvM]

Good that you solved the issue. Instead of appending multiple source files send .zip or project .qar.