I'm using Intel PAC N3000 provided hello_afu source code. I want to simulate this project with modelsim Intel FPGA edition. I try to use Quartus ➤Tools ➤ Generate Simulator Setup Script for IP to generate a .tcl file as what was done in section1.3, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf . But there is an error:
Error: SPD file ~/inteldevstack/rtl/pac_n3000_rtl_1.3.6/hello_afu/hw/pac/dcp_1.2-aim/design/fme/seu/ip/seu_sys/seu_sys_emr_unloader2_0/seu_sys_emr_unloader2_0.spd not found. Please generate simulation files for IP file ~/inteldevstack/rtl/pac_n3000_rtl_1.3.6/hello_afu/hw/pac/dcp_1.2-aim/design/fme/seu/ip/seu_sys/seu_sys_emr_unloader2_0.ip before generating simulator setup scripts.
There are 93 similar errors in total. Every .ip file provided in the source code folder needs a .spd file.
How can I generate simulation files for IP file? Please let me know how to do that if you can solve this problem. Thank you very much!
You cannot use the Generate Simulator Setup Script for IP....this is not an IP.
ASE simulation is also not supported.
You can simulate each functional unit like any RTL simulation you perform on Quartus.