Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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NIOS code address define

GDeXi
Beginner
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I have a 32MB SDRAM and NIOS is running on the FPGA. I hope that the space of 12MB in the back is used to store user data instead of Nios code. How can I define it in eclipse? Thank you.

 

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EricMunYew_C_Intel
Moderator
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The address map in Platform Designer indicates the memory range of your SDRAM.

You can refer to this memory range when you store data.


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