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Need Clarificaiton on Cyclone 10 GX Pin Tolerance Table

mindchasers
New Contributor I
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Looking at Table 99 of the Cyclone 10 GX Fabric and IO Handbook, I'm confused by the stated requirements for 3V IO banks. 

 

The table shows a '-' for "Drive to GND" and "Drive to VCCIO" for the Power Up condition. 

 

'-' means  Not Applicable. 

 

What's the requirement for this bank?  Is the table conveying that the 3V I/O pins can not have a voltage applied to them during power up, or does the '-' mean that there is no requirement and any voltage within the maximum and minimum are permitted?

 

Also, it's strange that app note AN692 discusses specifically the 1.8V I/O and transceiver I/O for an unpowered FPGA but leaves out 3V I/O.

 

Thanks

 

 

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Ash_R_Intel
Employee
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Hi,

The table is meant to depict the conditions when 'Hot-Scoketing' may be acceptable and what unpowered pins can tolerate.

The way I read the table is, for 3VIO banks 'Hot-Socketing' is Not Applicable. So, an unpowered 3VIO bank pin should NOT be driven to GND/VCCIO externally during power-up. During power-down, the unpowered pin and still be driven to GND but not VCCIO.

Hope this helps.


Regards.


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Ash_R_Intel
Employee
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We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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