Need help from Guru

Altera_Forum · ‎10-05-2010

Hey guys,

I am looking for some help in the syntax. Following is my syntax to perform a voting system.

Library IEEE;

USE IEEE.std_logic_1164.all;

Entity Gproject IS

PORT ( Se0, Se1, Se2, Se3 : IN std_logic;

Sn0, Sn1, Sn2, Sn3 : IN std_logic;

D : OUT std_logic_vector (6 downto 0);

Co : OUT std_logic;

L1, l2, L3 : OUT std_logic;

less : out std_logic;

equal : out std_logic;

greater : out std_logic);

End Gproject;

Architecture Vsystem OF Gproject IS

Component Attendance

PORT ( Se0, Se1, Se2, Se3 : IN std_logic;

S1, S2, Co : OUT std_logic);

END component;

Component AddSub

PORT( A, B :IN std_logic_vector(3 DOWNTO 0);

S :IN std_logic;

Co :OUT std_logic;

X :OUT std_logic_vector(3 DOWNTO 0));

END component;

Component Comparator

port( A : in std_logic_vector(3 downto 0);

B : in std_logic_vector(3 downto 0);

less : out std_logic;

equal : out std_logic;

greater : out std_logic);

end component;

Component SegmentDisplay

port( W :IN std_logic_vector (3 downto 0);

D :OUT std_logic_vector (6 downto 0));

End component;

Signal at: std_logic_vector (12 downto 5);

Signal X: std_logic_vector (3 downto 0);

Begin

at(5) <= '0';

at(9) <= '0';

X(3) <= '0';

Att : Attendance PORT MAP (Se0, Se1, Se2, Se3, at(6), at(7), at(8));

Display1 : SegmentDisplay PORT MAP (at(8 downto 5), D(6 downto 0));

Vsystem : Attendance PORT MAP (Sn0, Sn1, Sn2, Sn3, at(10), at(11), at(12));

Display2 : SegmentDisplay PORT MAP (at(12 downto 9), D(6 downto 0));

Add_Sub : AddSub PORT MAP (at(8 downto 5), at (12 downto 9), '1', Co, X(3 downto 0));

Compare : Comparator PORT MAP (at(12 downto 9), X(3 downto 0), less, equal, greater);

End Vsystem;

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I got the error msg

Error (10028): Can't resolve multiple constant drivers for net "X[3]" at Gproject.vhd(52)

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I do not understand and can't find where is my mistake. I hope anyone here would help me to answer my question.

Thanks

Altera_Forum · ‎10-05-2010

you're driving X(3) to '0', but you're also driving it from the output of the addsub.

You can only do one or the other.

Altera_Forum · ‎10-05-2010

Your are assigning X(3) twice:

- X(3) <= '0';

- output port of AddSub component

Altera_Forum · ‎10-05-2010

do you guys mind telling me how should I compute the syntax for this part?

BTW... I deleted the X(3) <= '0' then tried to compile...

NOW... new problems...

Error: Node instance "H1" instantiates undefined entity "H_adder"

(H_adder is one of the component I use in the blocks)

May I know what this means?

Thanks

Altera_Forum · ‎10-06-2010

The code that you showed doesn't have any H1 instantiation.

The most likely cause is that you forgot to declare the H_adder component in your architecture.

Altera_Forum · ‎10-06-2010

my problems have been solved.

thanks guys for the advices.