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I was trying to simulate my design. It compiled fine and I actually downloaded to the DE2-115 board and it worked as expected. When I try to simulate the design I keep getting this message. The problem seems to be in the error message at the bottom but I can not figure out what to do. Any help will be appreciated. Thank you
Determining the location of the ModelSim executable... Using: c:/intelfpga_lite/17.0/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** generating the modelsim testbench ****quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off dummy -c dummy --vector_source="C:/Users/marcu/Desktop/Fall 2017/Advanced Digital Design/DE2-115 Projects/Before_Class_Projects/dummy/Waveform.vwf" --testbench_file="C:/Users/marcu/Desktop/Fall 2017/Advanced Digital Design/DE2-115 Projects/Before_Class_Projects/dummy/simulation/qsim/Waveform.vwf.vht" Info: ************************************************** ***************** Info: Running Quartus Prime EDA Netlist Writer Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Intel and sold by Intel or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Mon Sep 04 11:45:46 2017 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off dummy -c dummy --vector_source="C:/Users/marcu/Desktop/Fall 2017/Advanced Digital Design/DE2-115 Projects/Before_Class_Projects/dummy/Waveform.vwf" --testbench_file="C:/Users/marcu/Desktop/Fall 2017/Advanced Digital Design/DE2-115 Projects/Before_Class_Projects/dummy/simulation/qsim/Waveform.vwf.vht" Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. error (199014): vector source file c:/users/marcu/desktop/fall 2017/advanced digital design/de2-115 projects/before_class_projects/dummy/waveform.vwf specified with --testbench_vector_input_file option does not exist
Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning error: peak virtual memory: 521 megabytes
Error: Processing ended: Mon Sep 04 11:45:47 2017 error: elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01 error.[/B][/B][/B][/B][/B][/B][/B][/B]
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It's saying you're missing your .vwf file.
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--- Quote Start --- It's saying you're missing your .vwf file. --- Quote End --- How can it say I am missing my vwf file when I created it? How does it not see it? Is there something in the settings I need to have?
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--- Quote Start --- It's saying you're missing your .vwf file. --- Quote End --- Also, from what I can see, it is only from the vwf file that I can simulate anything so it has to be created before attempting to do anything. Not sure what to do
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--- Quote Start --- Also, from what I can see, it is only from the vwf file that I can simulate anything so it has to be created before attempting to do anything. Not sure what to do --- Quote End --- Maybe that is not the exact path to where the .vwf file exists that you created? The path to the .vht file is slightly different.
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So I need a vht file?
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--- Quote Start --- So I need a vht file? --- Quote End --- I don't know, you tell me. You supplied a testbench filename in the --test_bench argument ... My point was that the full pathname to the .vht file is different from that to your .vwf file. Maybe that is ok, maybe not. I was just pointing that out as something to look at as it may be an issue as to why one file is flagged as 'missing'.
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