Hi, I have this Nios II Development Kit, Cyclone II Edition Board withEP2C35F672. In quartus 7.2, the device is reconized+can be programmed but when I do flash the program, it doesn't effect that board, and I don't see in changes in hardware, even in designing simple pin to pin wire. what could be the problem?, i'm programming in JTAG form (*.sof)
The are specific regions of flash where the hardware is expected to reside. Ensure you are using those regions otherwise the CPLD that is handling the flash configuration will not be able to program the image you want. These regions should be defined in the user guide for the board.If you are also seeing issues programming the .sof then make sure you either pull the reconfig_req_n signal high or set the unused I/O to input tri-state. Without doing one of these the first thing your design might be doing is pulling reconfig_req_n low which tells the MAX part to send in a new image from flash.