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I'm currently working on a Arria ii gx project involving the Nios processor and I've run into an issue with System ID and System timestamp mismatch errors. I've been unable to find a solution on my own, so I'm seeking your expertise to help me resolve this problem.
Description:
I have a Nios processor-based system that consists of various components, such as memory controllers, peripherals, and the Nios II processor itself. However, I've noticed that there is a mismatch in the System IDs between these components, causing communication and identification issues. Additionally, there is a discrepancy in the system timestamps, leading to synchronization problems.
I've reviewed my configuration files and settings for all the components involved, but I'm still unable to pinpoint the root cause. I've also tried adjusting the clock settings and enabling synchronization mechanisms, but the errors persist.
If anyone has encountered similar issues or has expertise in troubleshooting Nios processor systems, I would greatly appreciate your guidance. Any suggestions or insights on how to resolve the System ID and System timestamp mismatch errors would be highly valuable.
Thank you in advance for your help!
Best regards,
Nome
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Hi,
What is the Quartus version used? Also, could you share the screenshot of the mismatch seen?
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Hello
Thanks for your Reply
I have remove and create new nios processor qsys but error still there
Please help us Thanks
Best Regard
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Hi,
Do you have any latest update for this issue?
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Hi,
It seems more than just sysid error, was there any error in Quartus or Nios SBT during compilation?
Could you share your design for me to quick check?
Also, you could port this design in to your board and have a quick test:
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Thanks for your reply
I used hello world example i changed quartus window to Linux even i changed board but expected sysid base address not found all our cases i am using quartus 18.1
today hope i will share here my project qpr
Thanks
best regards
nome
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My issue has been resolved in platform design I missed to set nios_cpu_reset debug with all IP reset
Thanks
best regards
nome
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Hi,
Glad that resolves for you, in the future, you could refer to our Embedded Design Handbook pdf, and refer to the "Booting methods" chapter where it shows the design connections and settings examples:
https://www.intel.com/programmable/technical-pdfs/683689.pdf
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

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