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I tried to synthesise following code (straight from Altera manual for inferring RAM) to gauge the M20K performance.
It compiles fine and I see from the .pin reports that all the inputs/outputs are assigned to pins but there is no Fmax reported in the .sta. So what am I missing this time? thanks, Kusti
module top_level(
output reg q,
input d,
input write_address, read_address, input we, clk
);
reg mem ;
always @ (posedge clk) begin
if (we)
mem <= d;
q <= mem; // q doesn't get d in this clock cycle
end
endmodule
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Fmax is reported in the {project}.sta.rpt file, found in the output_files directory by default.
Cheers, Alex- Mark as New
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Thanks! Sorry, I did not make myself clear, this is what I have in .sta.rpt:
--------------------------------------
; Slow 900mV 100C Model Fmax Summary ;
--------------------------------------
No paths to report.
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That's because it can only time from register to register. Your design only has a single output register. You need to register the d and we inputs to get an fmax report.
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