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Altera_Forum
Honored Contributor I
2,394 Views

No clocks defined in design / Minimal verilog only example

Hi, 

 

I've been stuck at this for two days.  

 

First of I'm very new to Altera so this is probably something very  

simple but I just can't figure/google this one out. 

 

I've set up a simple project that compiles fine, except I get this "No clocks defined in design" error 

and thus cannot get the Fmax for my trial design. 

 

Obviously somehow the compiler does not understand that there is a clock used in 

my Verilog code or something, but I cannot figure out what to do. 

 

My verilog is like this: 

 

//--------------------------------------------------------------------- 

module correlator( 

input clk, 

input sys_rst 

); 

 

 

<snip> 

 

 

always @(posedge clk) begin 

 

 

<snip> 

//--------------------------------------------------------------------- 

 

This is my .qsf 

 

//--------------------------------------------------------------------- 

set_global_assignment -name FAMILY "Arria 10" 

set_global_assignment -name DEVICE 10AS066N3F40E2SG# set_global_assignment -name FAMILY "Cyclone 10 GX" 

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0 

set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:57:02 JANUARY 17, 2018" 

set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Pro Edition" 

set_global_assignment -name TOP_LEVEL_ENTITY correlator 

set_location_assignment PIN_G1 -to clk 

set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id clocka 

set_global_assignment -name DUTY_CYCLE 50 -section_id clocka 

set_instance_assignment -name CLOCK_SETTINGS clocka -to clk 

set_global_assignment -name BASED_ON_CLOCK_SETTINGS clocka -section_id clockb 

set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id clockb 

set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 2 -section_id clockb 

set_global_assignment -name DUTY_CYCLE 50 -section_id clockb 

set_global_assignment -name OFFSET_FROM_BASE_CLOCK "500 ps" -section_id clockb 

set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id clockb 

set_instance_assignment -name CLOCK_SETTINGS clockb -to clkx2 

set_instance_assignment -name MULTICYCLE 2 -from clk -to clkx2 

//--------------------------------------------------------------------- 

 

 

 

 

 

In my .sdc I have: 

 

//--------------------------------------------------------------------- 

create_clock -name {clk} -period 1.000 -waveform { 0.000 0.500 } [get_ports {clk}] 

create_clock -name {clkx2} -period 1.000 -waveform { 0.000 0.500 } [get_ports {clkx2}] 

//--------------------------------------------------------------------- 

 

 

 

I've copied those from the 'filtref' example from Quartus installation 

and that project compiles fine and produces Fmax, but that project 

has toplevel as schematic entry and I want/need Verilog/textfile only solution. 

 

I've tried to find a complete example project that would be Verilog with 

text only files but have not found one ... so a pointer would be highly 

appreciated. 

 

But the main question is how do I make Quartus recognize my clock? 

 

wbr Kusti
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5 Replies
Altera_Forum
Honored Contributor I
634 Views

check the warnings and ensure it hasnt removed all of your logic. This can often happen for several reasons: 

- Clock not connected, or stuck at 1/0 

- Reset always asserted 

- Input logic stuck at specific value, causing design to be optimised awa 

- Design having no effect on any outputs. 

 

If you have no outputs in the design that can connect to pins, then the whole design will be optimised away.
Altera_Forum
Honored Contributor I
634 Views

Thank you! 

 

 

--- Quote Start ---  

check the warnings and ensure it hasnt removed all of your logic. This can often happen for several reasons: 

- Clock not connected, or stuck at 1/0 

- Reset always asserted 

If you have no outputs in the design that can connect to pins, then the whole design will be optimised away. 

--- Quote End ---  

 

 

Thanks, I was thinking along those lines. But this is where I need some hand holding. 

 

Your write "If you have no outputs in the design that can connect to pins", this raises the question 

how to ensure that "outputs can connect to pins" ?  

 

Looking at my code I see that I actually have no outputs out of the module so indeed this can be the problem. 

 

I will change, test and report back. 

 

Your write " Clock not connected", this is also not clear to me how the clock should be connected, 

if you look at my code this is all I have: I have a signal 'input clk' and 'always @(posedge clk)', what else do I need to do to  

make the compiler understand that this is a clock.  

 

I've not specified in anyway (or have I?) how that 'clk' is connected ... should I and how to do that? 

 

Same confusion about the reset... as this is only meant as test case to gauge the FPGA speed and 

the speed of that design I don't know where to connect those at this point and/or how to set them 

so that I can get the Fmax out... 

 

wbr Kusti 

 

 

 

Altera_Forum
Honored Contributor I
634 Views

Your .sdc defines a clock targeting a port named clkx2 that does not exist in your code. Your .qsf shows clocks named clocka and clockb that aren't there either. I'm not sure what's going on here.

Altera_Forum
Honored Contributor I
634 Views

If your module was not the top level, and you connected the clock port to '1b1 or 1'b0, then it would be stuck at 1/0.  

If this module is your top level, you've already assigned the clk port to a pin, so it will be connected correctly, (and not stuck at 1/0).  

The lack of outputs is the problem. The compiler sees your design does nothing useful, and removes all the logic.
Altera_Forum
Honored Contributor I
634 Views

 

--- Quote Start ---  

If your module was not the top level, and you connected the clock port to '1b1 or 1'b0, then it would be stuck at 1/0.  

If this module is your top level, you've already assigned the clk port to a pin, so it will be connected correctly, (and not stuck at 1/0).  

The lack of outputs is the problem. The compiler sees your design does nothing useful, and removes all the logic. 

--- Quote End ---  

 

 

 

Thanks! All of this is was the information that I could not find from the documentation and what I needed. With the outputs defined it now works a treat! Thanks again!
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