Programmable Devices
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Not Able to Compile in Windows

m_kumar
New Contributor I
119 Views

I was using Quartus lite edition i trying to run small code but below error was coming, 

Error (293007): Current module quartus_map ended unexpectedly. Verify that you have sufficient memory available to compile your design. You can view disk space and physical RAM requirements on the System and Software Requirements page of the Intel FPGA website (http://dl.altera.com/requirements/).

Can you please help me with how to fix the issue.

Thanks & Regards 

Manoj 

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3 Replies
sstrell
Honored Contributor III
108 Views

Just as the message says.  What version of Quartus are you running?  What are the specs of your computer?  What device are you targeting and how big is the design?  "Small code" doesn't mean anything if it still ends up generating a lot of logic due to loops, generate commands, etc.  Are there any other error or warning messages?

m_kumar
New Contributor I
94 Views

Quartus version 20.1 and windows 10 8 GB RAM

i was targeting Max10 device.

No any other warning/issue

rtl code:

module hw_top ( input wire clock,
input wire areset_n,
output wire led1,
output wire led2);


reg [2:0] reset;
reg [24:0] count1;
wire count1_rst;

always@(posedge clock or negedge areset_n ) begin
if ( !areset_n ) begin
reset <= 3'b111;
end else begin
reset[0] <= 1'b0;
reset[2:1] <= reset[1:0];
end
end

always@(posedge clock or posedge reset[2] ) begin
if( reset[2] == 1'b1 ) begin
count1 <= 25'd0;
end else begin
if ( count1_rst ) begin
count1 <= 25'd0;
end else begin
count1 <= count1 + 1'd1;
end
end
end
assign count1_rst = ( count1 == 25'd24999999 ) ? 1'b1:1'b0;
assign led1 = ( count1 >25'd124999999 ) ?1'b1 :1'b0;
assign led2 = ~led1;
endmodule

SyafieqS
Moderator
92 Views

Kumar,


Can you try to look at below KDB if applicable, perhaps it helps.

https://www.intel.com/content/www/us/en/support/programmable/articles/000086648.html


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