I’m using a cyclone IV FPGA (EP4CE55F23C8N) and I’m outputting a 48Mhz clock signal (generated by the internal PLLs) that feeds a microcontroller. The problem is I’m not getting the required 3.3 voltage level (using the 3.3-V LVTTL and LVCOMS), I get 1 vpp (peak to peak) on my oscilloscope.
I figured the problem is related to the FPGA current limiting circuitry. So I dabbled with lower voltage values like 3v,2.5v which offer higher current limits. But still I wasn’t able to squeeze out sufficiently high logic levels. The best I got was around 1.4vpp. Also I activated the internal weak pull up resistor with no significant improvement from the voltage level standpoint.
Any thoughts on how I can generate the 3.3v full range.
What are the characteristics of your scope probe and input?
Is it a high impedance or 50ohm termination that you have on your probe?
What is the input bandwidth of your scope channel?
A CycloneIV with LVTTL or LVTTL 3.3V output should be able to drive a 4ma to 8ma load (depending on drive selected) 48MHz (20ns period) with a 2ns to 3ns rise/fall time pretty much rail to rail.
You are right. I think the issue had to do with the probe bandwidth as a function of the probe multiplier. I had my probe set to x1 multiplier (no amplification no attenuation) which reduces the BW to 5Mhz according to probe the datasheet. By setting the probe to x10 i get 100Mhz BW. I did my measurements (pic attached) i got 400~500mVpp which translates to 5vpp after accounting for the probe multiplier.
I hope the above ak6dn's suggestion may have addressed your question.
Do you have any further questions on this matter?
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