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Valued Contributor III
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Odd Counter Output.

Hello all; 

 

I am trying to learn AHDL and have run into a problem. I tried searching the forum, but could not find anything like what I am seeing. 

 

I am sure I have done something to the settings or something to cause the problem, because even with a new project I get the same results. The reason I think it is a setting is when I first simulated the code it worked correctly. I used it for a couple hours while using it in another file to compare it to so I could verify that my other code was working I started to get this output. It worked fine, but I never could get the other code to work right. I then made a new project and retyped the code, not just copied it with the same results.  

 

I have made a simple counter. Below is the code: 

 

SUBDESIGN TEST2 

clock :INPUT; 

Q[3..0] :OUTPUT; 

 

VARIABLE 

 

count[3..0] :DFF; 

 

BEGIN 

 

count[].clk = clock; 

count[].d = count[].q - 1; 

q[] = count[].q; 

 

END; 

 

 

I am not getting what I would expect, 15 to 0 repeating. What I am getting is this: 

 

15,7,11,3,13,5,9,1,14,6,10,2,12,4,8,0  

 

It keeps repeating. I did notice that all the numbers 0 to 15 are present. 

 

I am using Quartus II ver 9. 

 

Thanks for any help. 

 

Larry
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6 Replies
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Valued Contributor III

Re: Odd Counter Output.

Output is simply inverted. 

Try to change high and low levels and possibly reverse bit order and you'll get the right count. 

Cris
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Valued Contributor III

Re: Odd Counter Output.

Suggestion. 

 

If you don't yet know them, better to study Verilog or VHDL. 

AHDL is an old language not sure will be supported in the future.
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Valued Contributor III

Re: Odd Counter Output.

I second the recommendation to learn VHDL or Verilog. you cannot simulation AHDL in RTL form and lacks the portability and useful features of the other two. 

 

Was there any particular reason you picked AHDL? is your tutor stuck in the early 90s?
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Valued Contributor III

Re: Odd Counter Output.

To Larry: your counter works fine, but you have the wrong order in your simulation showing Q[0..3] rather than Q[3..0]. 

To Tricky: to a (self-)starter AHDL is much more intuitive then VHDL or Verilog. But is less high-level than the other 2, so nplttr's recommendation certainly is good advice.
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Valued Contributor III

Re: Odd Counter Output.

Thank you all for your replys. AHDL is wha the coures instuctor wants. I have heard that AHDL may be on its way out. When done with this course I will learn VHDL. 

 

I will give the suggestions a try. Thank you again.
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Valued Contributor III

Re: Odd Counter Output.

Thank you all for your replies. Cris72 and josyb where correct. In the .vwf file I had the MSB and LSB's reversed. Thank you both for your help. It saved me alot of trouble!!

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