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On-die capacitor and package parasitic for Cyclone V

SP87
Beginner
1,133 Views

Hello,

I am looking for a model or file which has the value of on-die decoupling capacitors on power pins of the Cyclone V FPGA.

I need this value of capacitor with ESR and ESL so as to correctly model the power pins for Power Integrity analysis of the board.

Thanks in advance.

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AqidAyman_Intel
Employee
1,089 Views

Hi,


Perhaps you can try to check on the Power Delivery Network (PDN) tool for Cyclone V Device. You need to download the zip file in the link below and open the spreadsheet. You can go to System_Decap tab and change the device family accordingly.


https://www.intel.com/content/www/us/en/content-details/657243/power-delivery-network-pdn-tool-2-0-for-stratix-v-arria-v-arria-ii-gz-cyclone-v-and-cyclone-iv-devices.html?wapkw=cyclone%20v%20pdn


Regards,

Aqid


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SP87
Beginner
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Hi Aqid,

Thank you for this reply. 

This is a very good tool to provide idea of PDN.

However, I am specifically looking for some information on decap value connected between BGA ball to die of the IC.

a small decoupling capacitor that we place inside IC package or a parasitic effect due to this

I am looking for IC power pin model to avoid Target impedance issues on frequencies beyond 200MHz

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FvM
Honored Contributor II
1,058 Views

Hi,
where did you get the idea that Cylone V has internal bypass capacitors? I'm no aware of an Intel document mentioning it. I doubt that there's room for capacitors in BGA package. 

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SP87
Beginner
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I also didn't found any information regarding this on datasheets.

I am mostly looking for any model that can support for actual on die parasitics to mitigate for > 200MHz decoupling of power supply noise in maintaining target impedance in FDTIM analysis. 

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AqidAyman_Intel
Employee
968 Views

Hi,


I also not sure if we have disclosed this information. So far, the only I can provide is the information that was included in the PDN as suggested earlier.


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