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OpenCL BSP for Stratix 10 GX Development Kit (H-Tile)

gustifix
Beginner
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Hello,

I want to get the Stratix 10 GX OpenCL BSP running on the Stratix 10 GX Development Kit (device part number: 1SG280HU2F50E2VG). It seems that the BSP reference platform targets the L-tile version (1SG280LU2F50E2VG). At least the top.sof file in $AOCL_BOARD_PACKAGE_ROOT/bringup specifies that device. Also, programming the max5_116.pof and flash.pof files works, but after a cold reboot the FPGA does not show up as a PCIe device, I assume because the bitstream in the flash targets the wrong device.

Is there a BSP available for the H-tile version of the dev kit or should I follow the porting guide to adjust the reference platform for a different device?

As the latest version of the BSP is 20.2, I am using that version of Quartus, the OpenCL SDK, and the BSP on Linux.

Regards,

Felix

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BoonBengT_Intel
Moderator
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Hi @gustifix,


Thank you for posting in Intel community forum and hope all is well.

Note as Intel OpenCL has been depreciated, hence the support that we can provide would be the best that we can.


Unfortunately, the S10GX BSP are for the mention H-tile version.

And yes you may following the porting guide mentioned, per my understanding different between H-tile and L-tile are just the transceiver variant, hence other should be good.

Hope that clarify


Best Wishes

BB


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BoonBengT_Intel
Moderator
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Hi @gustifix,


Thank you for posting in Intel community forum and hope all is well.

Note as Intel OpenCL has been depreciated, hence the support that we can provide would be the best that we can.


Unfortunately, the S10GX BSP are for the mention H-tile version.

And yes you may following the porting guide mentioned, per my understanding different between H-tile and L-tile are just the transceiver variant, hence other should be good.

Hope that clarify


Best Wishes

BB


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gustifix
Beginner
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Hi BB,

Thank you for the answer! After changing the device part number according to the guide, I had to slightly adjust the floorplan (just adding 10 to all the x coordinates in base.qsf seems sufficient) after I got some fitter errors.

Compiling the base revision works now, but timing slightly fails. I'm gonna compile it with various seeds until I get a result that meets timing requirements.

Best regards

Felix

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BoonBengT_Intel
Moderator
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Hi @gustifix,


Great! thanks for elaborating the details which helps us understand better, as for the timing related issues yes it could be solved by changing the seeds on some situation. However if issues persist, you may post the error faced in the 'Intel® Quartus® Prime Software' board and out timing expert will get back to you at earliest.


With no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

Thank you for the questions and as always pleasure having you here.


Best Wishes

BB


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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gustifix
Beginner
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Hi @BoonBengT_Intel,

Thanks for the help so far! After a few compiles with different seeds, I got a version that meets timing. I followed the porting guide further and now I have a top.sof file for the 1SG280HU2F50. When trying to program the file via the Quartus programmer, after clicking "Auto detect", I have to choose the exact device number:

Screenshot_20240304_105946.png

I choose 1SG280HU2 and get this chain:

Screenshot_20240304_110021.png

When I add top.sof, it shows up as a different device:

Screenshot_20240304_110611.png

If I delete the 1SG280HU2 so the chain looks like this:

Screenshot_20240304_123903.png

I get "Error status: Synchronization failed" when trying to program the device.

 

Does programming the sof directly just not work in this case and should I generate the pof for flash, or is there a way to program the FPGA this way?

Thanks and best regards

Felix

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gustifix
Beginner
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OK, generating the pof seems to be the right way. I followed this video to generate flash.pof from top.sof. The only change from the video was to set P1 of CFI_1Gb to 0x00200000 instead of 0x000D0000.

After a cold reboot, the device now shows up as "Processing accelerators: Altera Corporation Device 5170" in lspci.

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