Oscillator clock is not wired to main clock input (IO/GCLKi) on MAX EPM570

[Altera_Forum]

One circuit was incorrectly redesigned so that there is no connection from the oscillator to the GCLKi pin(s) on the CPLD. Since it is BGA package, GCLKi pin is not reachable, but some other pins are reachable through external components. My question is: Is it possible to connect GCLKi pin with internal signal (VHDL) to some reachable pin that is going to be wired to clock oscillator? Will that work and will the CPLD be clocked that way? 

 Something like this: library IEEE; use IEEE.STD_LOGIC_1164.all; entity y is  port (  PINx: in std_logic; --PINx is configured to be connected to accesible pin to which external clock is wired  LCLK: inout std_logic --LCLK is configured to be connected to GCLKi  ); end y;  architecture xA of x is signal clockReroute: std_logic; begin clockReroute <= PINx; --PINx is accesible pin to which external clock is wired LCLK <= clockReroute; end xA;   Thanks in advance for the answer.  Best regards.

[Altera_Forum]

Review the device handbook. 

You can use any I/O pin as clock input. Quartus will connect it to the global clock network. A respective time delay and delay skew will observed.  Did you ever try before starting this thread?