Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18988 Discussions

Our product need FPGA (10AX048E3F29E2SG) & CPU(i7-9700,i5-8400) exchange data through PCIe cable .We often happen device lost .Maybe restart computer ,everything is ok .So we think software about PCIe interface configure document need match. For Ex ,EQ

User1582077244785968
216 Views

De-emphsis ,EQ configure for CPU & FPGA need match .Thanks for your help.微信图片_20200217094658.jpg

0 Kudos
1 Reply
SengKok_L_Intel
Moderator
107 Views

Hi,

 

If you are using the cable, the SI may not be optimized:

 

  1. Is the Endpoint and Root Port uses the same physical reference clock? Did you enable the slot clock configuration in the PCIe IP?
  2. Is the LTSSM (capture the ltssmstate using signaltap) is looping between L0 and recovery continuously?
  3. Could you try to enable the soft DFE controller IP in the PCIe IP?

 

Regards -SK

 

Reply