Output Buffer - Megafunction ALTIOBUF

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Output Buffer - Megafunction ALTIOBUF

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Hello,

I'm using a Cyclone III device.

I want to output an LVDS clock around 100MHz. The frequency of the differential clock is not as much of a problem as the propagation delay induced by the output buffer.

I understand I have to instanciate a "global" output buffer between my clock signal and the output pad. I have two questions :

- How do specify the LVDS electrical format?

- What's a typical value for propagation delay for this ALTIOBUF function?

Thanks all!

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